The exemplary embodiments of this invention relate generally to semiconductor devices and techniques for the fabrication thereof and, more specifically, to the fabrication of fin-type transistor devices having channels of III-V materials.
Semiconductors and integrated circuit chips have become widely used in many products due to their decreasing cost and size. In the microelectronics industry there is a continued desire to reduce the size of structural features and microelectronic devices in order to provide a greater amount of circuitry on a given chip. Doing so generally allows for increased performance (more processing per clock cycle and less heat generated) at lower power levels and lower cost. However, the present technology is at or approaching atomic level scaling of certain micro-devices.
One type of microelectronic device that is continually being reduced in size is a field effect transistor (FET), which is generally defined by a source, a gate, and a drain. The action of the FET depends on the flow of majority carriers along a channel that runs past the gate and between the source and drain. Current through the channel between the source and drain may be controlled by a transverse electric field under the gate.
The size of a FET can be reduced by forming the channel in the shape of a fin. A FET employing such a channel structure may be referred to as a finFET. The fin-shaped channels (or “fins”) may be fabricated of, for example, germanium or III-V materials.
Such fins may be fabricated on silicon substrates. The fabrication of defect-free III-V fins on a silicon substrate, however, may be difficult. Current III-V heterogeneous epitaxy techniques (such as aspect ratio trapping and graded buffer growth) and other deposition techniques generally utilize relatively thick buffers of III-V materials (e.g., more than several hundreds of nanometers) and tend to result in the fabricated fins having large numbers of defects.